DIV=0, USGN=0, SQRT=0, DZE=0, BUSY=0, DZ=0, SRT=0, DFS=0, REM=0
Control/Status Register
| SRT | Start 0 (0): No operation initiated 1 (1): If CSR[DFS] = 1, then initiate a divide calculation, else ignore |
| USGN | Unsigned calculation 0 (0): Perform a signed divide 1 (1): Perform an unsigned divide |
| REM | REMainder calculation 0 (0): Return the quotient in the RES for the divide calculation 1 (1): Return the remainder in the RES for the divide calculation |
| DZE | Divide-by-Zero-Enable 0 (0): Reads of the RES register return the register contents 1 (1): If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned |
| DZ | Divide-by-Zero 0 (0): The last divide operation had a non-zero divisor, that is, DSOR != 0 1 (1): The last divide operation had a zero divisor, that is, DSOR = 0 |
| DFS | Disable Fast Start 0 (0): A divide operation is initiated by a write to the DSOR register 1 (1): A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 |
| SQRT | SQUARE ROOT 0 (0): Current or last MMDVSQ operation was not a square root 1 (1): Current or last MMDVSQ operation was a square root |
| DIV | DIVIDE 0 (0): Current or last MMDVSQ operation was not a divide 1 (1): Current or last MMDVSQ operation was a divide |
| BUSY | BUSY 0 (0): MMDVSQ is idle 1 (1): MMDVSQ is busy performing a divide or square root calculation |